1. Field of the Invention
The present invention relates to a wireless communication system. More particularly, the present invention relates to an apparatus and method for scrambling in a wireless communication system.
2. Description of the Related Art
In a wireless communication system, an information bit stream forwarded from a transmit end to a receive end is converted into symbols through encoding and modulation, is converted into a signal of a Radio Frequency (RF) band according to a physical layer standard of a system, and then is transmitted. At this time, the information bit stream is divided into a size of a constant unit, and is Cyclic Redundancy Check (CRC) processed. The CRC processing is a procedure for determining the occurrence or non-occurrence of a transmission error by performing a polynomial operation using a predefined CRC code in the transmit end and the receive end. If transmission bits are all equal to ‘0’, a result of CRC processing of the receive end is equal to ‘0’. However, even if bits all of which are not equal to ‘0’ are transmitted but all are not received due to channel deterioration, a result of CRC processing of the receive end is equal to ‘0’. That is, although all the transmission bits are lost due to the channel deterioration, the receive end erroneously determines that there is no transmission error.
Accordingly, in order to detect a case in which transmission bits are all equal to ‘0’, the transmit end and the receive end perform scrambling and descrambling. In general, the scrambling is performed through a scrambler that is comprised of a shift register. After that, a scrambled bit stream is converted into symbols. At this time, number of bits necessary to generate one symbol is varied depending on a modulation scheme. For example, a Binary Phase Shift Keying (BPSK) scheme needs one bit per symbol, a Quadrature Phase Shift Keying (QPSK) scheme needs two bits per symbol, and a 16 Quadrature Amplitude Modulation (16QAM) scheme needs four bits per symbol.
However, the scrambler has an input of a bit unit and an output of a bit unit. That is, bits of length ‘N’ number are input in sequence, and scrambled bits of length ‘N’ number are output in sequence. Thus, a high order modulation scheme of more than a QPSK scheme requires buffering bits of number necessary to generate each symbol. And, the buffering causes an increase of a processing time consumed to transmit a transmission bit stream.
As described above, because of the bit-unit input/output of the scrambler, a modulation scheme of mapping a plurality of bits per symbol requires buffering. Further, as a modulation order increases, a processing time consumed due to the buffering increases. Because of this, it is required to decrease a time consumed for a different operation or increase an operation clock of the scrambler in order to meet with a signal processing time required by a system. Thus, there is a need for an alternative for reducing the processing time consumed due to the buffering.